Native support of Verilog, SystemVerilog for design, VHDL, and SystemC for effective verification of sophisticated design environmentsįast time-to-debug, easy to use, multi-language debug environmentĪdvanced code coverage and analysis tools for fast time to coverage closure Unified mixed language simulation engine for ease of use and performance The best standards and platform support in the industry make it easy to adopt in the majority of process and tool flows. The combination of industry-leading, native SKS performance with the best integrated debug and analysis environment make ModelSim® the simulator of choice for both ASIC and FPGA designs. Mentor Graphics was the first to combine single kernel simulator (SKS) technology with a unified debug environment for Verilog, VHDL, and SystemC.
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